Multistage Decimators with Minimum Group Delay

被引:0
|
作者
Pasolini, Gianni [1 ]
Soloperto, Raffaele [1 ]
机构
[1] Univ Bologna, DEIS, CNR, WiLab,IEIIT BO, I-40136 Bologna, Italy
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper we face the issue of the most effective implementation of multistage decimators in terms of group delay minimization. Here we derive the design criteria to minimize the group delay of multistage decimators and we check their validity comparing the analytical outcomes with the "experimental" outcomes obtained through the design of a variety of decimators.
引用
收藏
页数:6
相关论文
共 50 条