Sub-1 V Output-Capacitor-less Low-Dropout Regulator with Two Compensation Amplifiers for Enhanced Power Supply Rejection

In this paper we propose two methods to boost the power supply rejection (PSR) of an output-capacitor-less low-dropout regulator (LDO). Our LDO is targeted for low-power system-on-chip applications, such as medical electronics, RFIDs, and IoT devices, where applied energy harvesting techniques induce large voltage ripple to supply line, thus requiring high PSR out of the LDO. The regulator utilizes a feed-forward path through the amplifier power supply rail to pass-transistor gate. Furthermore it includes a feed-forward amplifier to improve the frequency response and a feedback amplifier to stabilize the LDO, eliminating the need for an area consuming compensation capacitor. The proposed LDO is implemented in 28-nm CMOS technology. It supplies 700-mV output level with a current range of 0-5 mA and a 100-mV dropout voltage. The three amplifiers within our LDO consume only a total of 13 mu A, thus regardless of increased complexity, high current efficiency of 99.74% is maintained. At the nominal load of 1 mA, low-frequency PSR reaches a value of -97 dB and at the high-frequency range of 1-20 MHz PSR is boosted to remain below -20 dB and the region of 3-10 MHz below -30 dB.