Hardware accelerators for Cartesian genetic programming

被引：0
|
作者：
Vasicek, Zdenek [1 ]
Sekanina, Lukas [1 ]
机构：
[1] Brno Univ Technol, Fac Informat Technol, Bozetechova 2, Brno 612664, Czech Republic
来源：
GENETIC PROGRAMMING, PROCEEDINGS | 2008年 / 4971卷
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP). The accelerators contain a genetic engine which is reused in all applications. Candidate programs (circuits) are evaluated using application-specific virtual reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed. The first one is devoted for symbolic regression problems over the fixed point representation. The second one is designed for evolution of logic circuits. In both cases a significant speedup of evolution (30-40 times) was obtained in comparison with a highly optimized software implementation of CGP. This speedup can be increased by creating multiple fitness units.
引用
收藏
页码：230 / +
页数：2
相关论文
共 50 条
  • [41] Visualisation and Analysis of Genetic Records Produced by Cartesian Genetic Programming
    Sekanina, Lukas
    Kapusta, Vlastimil
    PROCEEDINGS OF THE 2016 GENETIC AND EVOLUTIONARY COMPUTATION CONFERENCE (GECCO'16 COMPANION), 2016, : 1411 - 1418
  • [42] Hardware real-time individualised blood glucose predictor generator based on grammars and cartesian genetic programming
    Cano, Jorge
    Hidalgo, J. Ignacio
    Garnica, Óscar
    Genetic Programming and Evolvable Machines, 2025, 26 (01)
  • [43] Neutral genetic drift: an investigation using Cartesian Genetic Programming
    Turner, Andrew James
    Miller, Julian Francis
    GENETIC PROGRAMMING AND EVOLVABLE MACHINES, 2015, 16 (04) : 531 - 558
  • [44] Neutral genetic drift: an investigation using Cartesian Genetic Programming
    Andrew James Turner
    Julian Francis Miller
    Genetic Programming and Evolvable Machines, 2015, 16 : 531 - 558
  • [45] Evolvable hardware using genetic programming
    Nedjah, N
    Mourelle, LD
    INTELLIGENT DATA ENGINEERING AND AUTOMATED LEARNING, 2003, 2690 : 321 - 328
  • [46] Kernel-as-a-Service: A Serverless Programming Model for Heterogeneous Hardware Accelerators
    Pfandzelter, Tobias
    Dhakal, Aditya
    Frachtenberg, Eitan
    Chalamalasetti, Sai Rahul
    Emmot, Darel
    Hogade, Ninad
    Enriquez, Rolando Pablo Hong
    Rattihalli, Gourav
    Bermbach, David
    Milojicic, Dejan
    PROCEEDINGS OF THE 24TH ACM/IFIP INTERNATIONAL MIDDLEWARE CONFERENCE, MIDDLEWARE 2023, 2023, : 192 - 206
  • [47] Weight Programming in DNN Analog Hardware Accelerators in the Presence of NVM Variability
    Mackin, Charles
    Tsai, Hsinyu
    Ambrogio, Stefano
    Narayanan, Pritish
    Chen, An
    Burr, Geoffrey W.
    ADVANCED ELECTRONIC MATERIALS, 2019, 5 (09):
  • [48] Recurrent Cartesian Genetic Programming of Artificial Neural Networks
    Turner, Andrew James
    Miller, Julian Francis
    GENETIC PROGRAMMING AND EVOLVABLE MACHINES, 2017, 18 (02) : 185 - 212
  • [49] Evolution of Neural Networks using Cartesian Genetic Programming
    Khan, Maryam Mahsal
    Khan, Gul Muhammad
    Miller, Julian F.
    2010 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION (CEC), 2010,
  • [50] Approximation of Digital Circuits Using Cartesian Genetic Programming
    Babu, Kagana Sarath
    Balaji, N.
    PROCEEDINGS OF THE 2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND ELECTRONICS SYSTEMS (ICCES), 2016, : 381 - 386
12345