Hardware accelerators for Cartesian genetic programming

被引：0
|
作者：
Vasicek, Zdenek [1 ]
Sekanina, Lukas [1 ]
机构：
[1] Brno Univ Technol, Fac Informat Technol, Bozetechova 2, Brno 612664, Czech Republic
来源：
GENETIC PROGRAMMING, PROCEEDINGS | 2008年 / 4971卷
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP). The accelerators contain a genetic engine which is reused in all applications. Candidate programs (circuits) are evaluated using application-specific virtual reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed. The first one is devoted for symbolic regression problems over the fixed point representation. The second one is designed for evolution of logic circuits. In both cases a significant speedup of evolution (30-40 times) was obtained in comparison with a highly optimized software implementation of CGP. This speedup can be increased by creating multiple fitness units.
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页码：230 / +
页数：2
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