A novel CMOS compatible embedded nonvolatile memory with zero process adder

被引：2

作者：

Breitwisch, MJ ^{[1
]}

Johnson, JB ^{[1
]}

Mittl, SW ^{[1
]}

Zhu, JW ^{[1
]}

Lam, CH ^{[1
]}

机构：

[1] IBM Corp, Div Res, Yorktown Hts, NY 10598 USA

来源：

2005 IEEE International Workshop on Memory Technology, Design, and Testing - Proceedings | 2005年

关键词：

D O I：

10.1109/MTDT.2005.12

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We demonstrate a CMOS compatible reprogrammable nonvolatile memory cell using a regular n-channel MOSFET with under-lapped source/drain diffusions that requires no extra processing steps in a standard 130nm CMOS logic technology. Experimental results indicate good endurance and retention characteristics. A strategy for optimizing programming efficiency is identified with the addition of one extra mask to introduce drain optimization implants.

引用

页码：9 / 12

页数：4

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