Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-standby and Instant-powerup Embedded Memory on IoT

In this paper, we propose a nonvolatile SRAM (NVSRAM) using the Fishbone-in-Cage Capacitor (FiCC) fabricated in a 0.18 mu m CMOS process technology. The FiCC can be implemented with metal wires as same as a metal-insulator-metal (MIM) capacitor that can be fabricated with a standard CMOS process technology. Three transistors and an FiCC are added to a conventional 6-transistor SRAM for non-volatile operations with 42% area overheads. Assuming 5 minutes active time per hour, the proposed NVSRAM can reduce 61.8% of power consumption compared with a standard SRAM. The fabricated NVSRAM can operate correctly as an SRAM at 100 MHz and perform nonvolatile store and restore operations by using the FiCC.