A nature inspired optimization algorithm for VLSI fixed-outline floorplanning

VLSI floorplan optimization problem aim to minimize the following measures such as, area, wirelength and dead space (unused space) between modules. This paper proposed a method for solving floorplan optimization problem using Genetic Algorithm which is named as 'Lion Optimization Algorithm' (LOA). LOA is developed for non-slicing floorplans having soft modules with fixed-outline constraint. Although a number of GAs are developed for solving VLSI floorplan optimization problems, they are using weighted sum approach with single objective optimization and crossover between two B*tree structure is not yet attempted. This paper explains, power of B*tree crossover operator for multiobjective floorplanning problem. This operator introduces additional perturbations in initial B*tree structure to create two new different B*tree structures compared with classical GA approach. Simulation results on Microelectronics Center of North Carolina and Gigascale Systems Research Center benchmarks indicate that LOA floorplanner achieves significant savings in wirelength and area minimization also produces better results for dead space minimization compared to previous floorplanners.