High-Speed Decoder Design using Memristor-Based Nano-Crossbar Architecture

Recent advances in physical implementation of the fourth circuit element, memristor, have opened up many promising applications of this device in versatile areas such as neuromorphic systems, memory, and logic design. One way to build logic circuits is to use a regular array of memristor-crossbar that can be configured to implement the required Boolean functions. In this work, the design for a decoder circuit is described using memristor-based nanoscale crossbar architecture. The delay of the proposed circuit is observed to grow linearly with the number of inputs compared to the exponential delay experienced in earlier designs. The proposed design is validated using NgSpice simulation.