Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis

被引：0
|
作者：
Lu, Tianyi [1 ]
Yin, Shouyi [1 ]
Yao, Xianqing [1 ]
Xie, Zhicong [1 ]
Liu, Leibo [1 ]
Wei, Shaojun [1 ]
机构：
[1] Tsinghua Univ, Beijing, Peoples R China
来源：
FPGA'17: PROCEEDINGS OF THE 2017 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS | 2017年
关键词：
Modulo Scheduling; Memory Partitioning; Multi-bank; HLS;
D O I：
10.1145/3020078.3021778
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：290 / 290
页数：1
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