Prototype for the Trigger-Less Data Acquisition of the PANDA Experiment 2014 IEEE Real Time Conference

The PANDA detector at the future FAIR facility in Darmstadt, Germany will operate with a very high anti-proton interaction rate of up to 2 x 10(7)/s in a free streaming mode without hardware triggers. Several hundreds of GB/s of data have to be read out. Sophisticated event filtering mechanisms based on tracking, calorimetry and particle identification are required in order to reject background events and reducing the amount of raw data by three orders of magnitude. This goal can be achieved by full event reconstruction and filtering in a highly parallelized and pipelined architecture including Field Programmable Gate Array (FPGA) platforms as well as Graphics Processing Units and PC farms. In this contribution, we present a prototype setup consisting of up to 4 FPGA based Compute Nodes, xTCA (extended Telecommunications Computing Architecture) compliant boards with a microTCA form factor, featuring a Xilinx Virtex 5FX70T-2 FPGA, 2 x 2 GB DDR2, 1 Gb Ethernet, and 4 SFP+ (Small Form-Factor Pluggable) interfaces. This subsystem will be driven by up to 9 data concentrators receiving data from sub-detector front-end electronics. The data is formatted into sub-events. Synchronization is achieved by matching SODANET (Synchronization of Data Acquisition) time stamps distributed to all sub-systems. Sub-events are subsequently combined to events that are transmitted to a server farm for further processing and mass storage. Each step of the Data Acquisition chain features optional event filtering.