Design of an SCL logic based Current Comparator

This paper presents a current comparator based on Source Coupled Logic (SCL) style and its variant called Positive Feedback Source Coupled Logic (PFSCL). It uses three stages namely current to voltage converter, SCL inverter and a PFSCL inverter. The proposed comparator functionality is examined through simulations using 0.18 mu m TSMC CMOS technology parameters. The propagation delay, resolution and power consumption are found as 0.8ns, +/- 10nA and 28 mu W respectively with an offset of 0.20mV. Process corner analysis and Monte Carlo Simulations have also been included to evaluate performance of the proposal with respect to transistor mismatches. Post layout simulations have also been carried out to validate the performance of the proposed current comparator.