Triple modular redundancy on parallel-operation-oriented optically reconfigurable gate arrays

被引：0
|
作者：
Ito, Yoshizumi [1 ]
Watanabe, Minoru [1 ]
机构：
[1] Shizuoka Univ, Elect & Elect Engn, 3-5-1 Johoku, Hamamatsu, Shizuoka 4328561, Japan
来源：
2015 IEEE INTERNATIONAL CONFERENCE ON SPACE OPTICAL SYSTEMS AND APPLICATIONS (ICSOS) | 2015年
关键词：
D O I：
暂无
中图分类号：
O43 [光学];
学科分类号：
070207 ; 0803 ;
摘要：
Recently, to realize autonomous functions resembling those of humans on space systems, higher-performance embedded systems than those of current space systems are necessary for use in long-distance space missions. Currently, a parallel-operation-oriented optically reconfigurable gate array (ORGA) has been under development. The ORGA can support a nanosecond-order high-speed reconfiguration and high-density implementation of parallel operations. The parallel-operation-oriented ORGA has many programmable gate array layers, which share a common configuration context and increase the number of implementable parallel operations. Therefore, a parallel-operation-oriented ORGA is suitable for hardware acceleration of a software operation on a processor. However, in a space environment, triple modular redundancy (TMR) must be used. Single common configuration memory becomes a weak point for radiation in terms of redundancy. Therefore, we propose a TMR implementation method that is suitable for the parallel-operation-oriented ORGA.
引用
收藏
页数：6
相关论文
共 31 条
  • [21] Architecture-Independent Negative Logic Implementation for Optically Reconfigurable Gate Arrays
    Fujimori, Takumi
    Watanabe, Minoru
    PROCEEDINGS OF 2016 7TH INTERNATIONAL CONFERENCE ON MECHANICAL AND AEROSPACE ENGINEERING, (ICMAE), 2016, : 381 - 385
  • [22] FPGA Hardware Accelerator for Holographic Memory Calculations for Optically Reconfigurable Gate Arrays
    Ito, Yoshizumi
    Watanabe, Minoru
    2017 IEEE INTERNATIONAL CONFERENCE ON SPACE OPTICAL SYSTEMS AND APPLICATIONS (ICSOS), 2017, : 146 - 149
  • [23] Recovery method for a laser array failure on Dynamic Optically Reconfigurable Gate Arrays
    Seto, Daisaku
    Watanabe, Minoru
    2010 IEEE 25TH INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS (DFT 2010), 2010, : 411 - 419
  • [24] An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays
    Mabuchi, Takayuki
    Watanabe, Minoru
    PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, 2008, : 289 - 292
  • [25] Optically Reconfigurable Gate Array VLSI That Can Support a Perfect Parallel Configuration
    Goto, Sae
    Watanabe, Minoru
    Watanabe, Nobuya
    2022 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS, 2022, : 241 - 245
  • [26] Photodiode sensitivity measurement methodology using low light intensity for optically reconfigurable gate arrays
    Ramanathan, Bharat
    Watanabe, Minoru
    2016 11TH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE & EDUCATION (ICCSE), 2016, : 454 - 457
  • [27] OPTMR: Optimal Data Flow Graph Partitioning for Triple Modular Redundancy Against Hardware Trojan in Reconfigurable Hardware
    Mao, Shengyang
    Liu, Leibo
    PROCEEDINGS 2016 IEEE 6TH INTERNATIONAL CONFERENCE ON ELECTRONICS INFORMATION AND EMERGENCY COMMUNICATION (ICEIEC), 2016, : 68 - 71
  • [28] A systematic design of fault tolerant systolic arrays based on triple modular redundancy in time-processor space
    Kaneko, M
    Miyauchi, H
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1996, E79D (12) : 1676 - 1689
  • [29] Link sharing scheme for fault tolerant systolic arrays based on mixed spatial-temporal triple modular redundancy
    Kaneko, M
    Miyauchi, H
    Park, CS
    APCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96, 1996, : 472 - 475
  • [30] Formation of holographic polymer-dispersed liquid crystal memory by angle-multiplexing recording for optically reconfigurable gate arrays
    Ogiwara, Akifumi
    Watanabe, Minoru
    APPLIED OPTICS, 2015, 54 (36) : 10623 - 10629
1234