TESTLINE: An IEEE P1500 compatible test scheme for SoC test

被引：0
|
作者：
He, H [1 ]
Sun, YH [1 ]
机构：
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/ICASIC.2003.1277553
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An IEEE P1500 compatible test scheme. TESTLINE, for modular SoC testing is presented in this paper. The test scheme consists of wrappers, TAM and User Defined Controller (UDC). For a given SoC, with specified parameters of modules and their tests, TESTLINE can optimize the testing time for the whole SoC using Integer Linear Programming (ILP). The ILP can efficiently determine the width of TAM and the assignment of modules to TAM. Experimental results for the 'ITC '02 SOC Test Benchmarks' show that TESTLINE is an effective and efficient test scheme for SoC testing.
引用
下载
收藏
页码：323 / 326
页数：4
相关论文
共 50 条
  • [31] Automating IEEE 1500 Core Test-An EDA Perspective
    Chakravadhanula, Krishna
    Chickermane, Vivek
    IEEE DESIGN & TEST OF COMPUTERS, 2009, 26 (03): : 6 - 15
  • [32] Enhancement in IEEE 1500 Standard for at-speed Test and Debug
    Ali, Ghazanfar
    Hussini, Fawnizu Azmadi
    Ali, Noohul Basheer Zain
    Hamidi, Nor Hisham
    Adnan, Raja Mahmud
    2014 IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE (IEEE DCAS 2014), 2014,
  • [33] Synthesizable Time Measurement and Test Scheme for SoC Architecture
    Abas, M. Amir
    MINO'09: PROCEEDINGS OF THE 8TH WSEAS INTERNATIONAL CONFERENCE ON MICROELECTRONICS, NANOELECTRONICS, OPTOELECTRONICS: ADVANCES IN MICROELECTRONICS, NANOELECTRONICS AND OPTOELECTRONICS, 2009, : 25 - 31
  • [34] Oscillation ring based interconnect test scheme for SOC
    Li, Katherine Shu-Min
    Lee, Chung Len
    Su, Chauchin
    Chen, Jwu E.
    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 184 - 187
  • [35] Study of an efficient SOC test vector compression scheme
    Key Lab. of Wide Band-gap Semiconductor Materials and Devices, Xidian Univ., Xi'an 710071, China
    Xi'an Dianzi Keji Daxue Xuebao, 2006, 1 (1-4+10):
  • [36] SOC Test Compression Scheme Sharing Free Variables in Embedded Deterministic Test Environment
    Wang Weizheng
    Cai Shuo
    Xiang Lingyun
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15 (03) : 397 - 403
  • [37] Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression
    Harpreet Vohra
    Amardeep Singh
    Journal of Electronic Testing, 2016, 32 : 735 - 747
  • [38] Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression
    Vohra, Harpreet
    Singh, Amardeep
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2016, 32 (06): : 735 - 747
  • [39] An SoC based Cost Effective Static Linearity Test Scheme for ADCs
    Manda, P. R. R. K. Tirumalesu
    Rai, Keerthan
    2023 IEEE INTERNATIONAL TEST CONFERENCE INDIA, ITC INDIA, 2023,
  • [40] New built-in self-test scheme for SoC interconnect
    Jutman, Artur
    Ubar, Raimund
    Raik, Jaan
    WMSCI 2005: 9TH WORLD MULTI-CONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL 4, 2005, : 19 - 24
12345