A Comparative Study of Metamodels for Fast and Accurate Simulation of Nano-CMOS Circuits

Fast simulation is a bottleneck for design space exploration of complex nanoscale CMOS (nano-CMOS) analog and mixed-signal (AMS) circuits. This paper presents the use of "metamodels" for fast and accurate AMS circuit design exploration. A design process flow that uses metamodels is introduced. Metamodel generation is the most time-consuming step of the design flow. Consequently, accurate and fast sampling of the design space is essential for the creation of the metamodel. Different sampling techniques are investigated to minimize the number of samples required. This paper uses two nanoscale CMOS analog circuits: a 45-nm ring oscillator and a 180-nm LC-VCO, as case studies. It is observed that the parasitics generated from the physical design of the circuits have a drastic effect on their performance metrics, such as frequency. Four alternative sampling techniques, both random [Monte Carlo (MC)] and uniform [Latin hypercube sampling (LHS), middle Latin hypercube sampling (MLHS), and design of experiments (DOEs)], are considered and compared for speed and accuracy. This paper provides a thorough exploration of these sampling techniques to determine which one is more suitable to minimize sampling size for metamodel generation and optimize the design cycle. Experiments show that LHS sampling is best for both circuits, followed by MLHS, MC, and DOE. In this paper, it is also shown that polynomial metamodels of order higher than two (which are commonly used) provide best accuracy.