Automatic synthesis of cache-coherence protocol processors using Bluespec

There are few published examples of the proof of correctness of a cache-coherence protocol expressed in an HDL. A designer generally shows the correctness of a protocol where many implementation details have been abstracted away. Abstract protocols are often expressed as a table of rules or state transition diagrams with an (implicit) model of atomic actions. There is enough of a semantic gap between these high-level abstract descriptions and HDLs that the task of showing the correctness of an implementation of a verified abstract protocol is as daunting as proving the abstract protocol's correctness in the first place. The main contribution of this paper is to show that this problem can be largely avoided by expressing the verified abstract protocol in Bluespec System Verilog (BSV), which is based on guarded atomic actions and is synthesizable into efficient hardware. Consequently, once a protocol has been verified at the rules-level, little verification effort is needed to verify the implementation. We illustrate our approach by synthesizing a non-blocking MSI cache-coherence protocol for Distributed Memory Systems and discuss the performance of the resulting implementation.