Efficient hardware controller synthesis for synchronous dataflow graph in system level design

被引：0

作者：

Jung, H ^{[1
]}

Lee, K ^{[1
]}

Ha, S ^{[1
]}

机构：

[1] Seoul Natl Univ, Sch Comp Sci & Engn, Seoul 151742, South Korea

来源：

13TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS, PROCEEDINGS | 2000年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow graph represents a hardware library module that contains a synthesizable VHDL code. Our proposed technique automatically synthesizes a clever control structure, cascaded counter controller, that supports asynchronous interaction with outside modules while efficiently implementing the synchronous dataflow semantics of the graph at the same time. Through comparison with previous work with some examples, the novelty of the proposed technique is demonstrated.

引用

页码：79 / 84

页数：6

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