Feature Selection for Waiting Time Predictions in Semiconductor Wafer Fabs

被引:2
|
作者
Schelthoff, Kai [1 ]
Jacobi, Christoph [2 ]
Schlosser, Eva [2 ]
Plohmann, David [2 ]
Janus, Michel [1 ]
Furmans, Kai [2 ]
机构
[1] Robert Bosch GmbH, RtP1 MFD2 SCO Dept, D-72762 Reutlingen, Germany
[2] Karlsruhe Inst Technol, Inst Mat Handling & Logist, D-76131 Karlsruhe, Germany
关键词
Production; Queueing analysis; Predictive models; Semiconductor device modeling; Feature extraction; Analytical models; Task analysis; Semiconductor manufacturing; high product-mix low-volume; feature selection; waiting time prediction; random forest regression; machine learning; permutation feature importance; JOB CYCLE TIME; ENSEMBLE;
D O I
10.1109/TSM.2022.3182855
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Based on real operational data from the Robert Bosch GmbH, we investigate influencing features for waiting time estimation of operations in high product-mix / low-volume semiconductor manufacturing fabs. We define waiting time as the elapsed time between completing the previous operation and starting the next one. In addition to well-established features, we introduce novel features to capture the complexity of the manufacturing environment. To the best of our knowledge, we are the first to attempt waiting time estimation in a high product-mix / low-volume semiconductor fab. We present a framework for feature selection which is composed of three steps: First, random forest models are trained for each operation. Second, a permutation feature importance (PFI) for the full set of features for each operation is computed and the performance is statistically evaluated. The optimal subset of features is then chosen by a sequential backward search based on the PFI values. Third, the performance in terms of the coefficient of determination of each optimized model is evaluated by means of the initial performance. We apply the framework to real operational data from the production areas Lithography and Diffusion and conclude that the feature set can be reduced significantly, while the prediction performance remains equal. The novel features are found to be frequently used when estimating waiting times in the investigated use case.
引用
收藏
页码:546 / 555
页数:10
相关论文
共 50 条
  • [21] Efficient simulations for capacity analysis and automated material handling system design in semiconductor wafer fabs
    Jimenez, JA
    Mackulak, G
    Fowler, J
    Proceedings of the 2005 Winter Simulation Conference, Vols 1-4, 2005, : 2157 - 2161
  • [22] A simulation-based two-stage scheduling methodology for controlling semiconductor wafer fabs
    Hu, Hongtao
    Zhang, Huai
    EXPERT SYSTEMS WITH APPLICATIONS, 2012, 39 (14) : 11677 - 11684
  • [23] Key Feature Identification for Monitoring Wafer-to-Wafer Variation in Semiconductor Manufacturing
    Fan, Shu-Kai S.
    Hsu, Chia-Yu
    Tsai, Du-Ming
    Chou, Mabel C.
    Jen, Chih-Hung
    Tsou, Jen-Hsuan
    IEEE TRANSACTIONS ON AUTOMATION SCIENCE AND ENGINEERING, 2022, 19 (03) : 1530 - 1541
  • [24] Shop-floor scheduling of semiconductor wafer fabs: Exploring the influence of technology, market, and performance objectives
    Sloan, TW
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2003, 16 (02) : 281 - 289
  • [25] Using in-line equipment condition and yield information for maintenance scheduling and dispatching in semiconductor wafer fabs
    Sloan, TW
    Shanthikumar, JG
    IIE TRANSACTIONS, 2002, 34 (02) : 191 - 209
  • [26] Optimising the location of crossovers in conveyor-based automated material handling systems in semiconductor wafer fabs
    Hong, Soondo
    Johnson, Andrew L.
    Carlo, Hector J.
    Nazzal, Dima
    Jimenez, Jesus A.
    INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH, 2011, 49 (20) : 6199 - 6226
  • [27] Levels of Capacity and Material Handling System Modeling for Factory Integration Decision Making in Semiconductor Wafer Fabs
    Jimenez, Jesus A.
    Mackulak, Gerald T.
    Fowler, John W.
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2008, 21 (04) : 600 - 613
  • [28] Effects of dispatching and down time on the performance of wafer fabs operating under theory of constraints
    Kayton, D
    Teyner, T
    Schwartz, C
    Uzsoy, R
    NINETEENTH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM - PROCEEDINGS, 1996 IEMT SYMPOSIUM, 1996, : 49 - 56
  • [29] Dynamic scheduling rule selection for semiconductor wafer fabrication
    Hsieh, BW
    Chang, SC
    Chen, CH
    2001 IEEE INTERNATIONAL CONFERENCE ON ROBOTICS AND AUTOMATION, VOLS I-IV, PROCEEDINGS, 2001, : 535 - 540
  • [30] Cost and cycle time performance of fabs based on integrated single-wafer processing
    Wood, SC
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1997, 10 (01) : 98 - 111