Sign bit reduction encoding for low power applications

被引：0

作者：

Saneei, M ^{[1
]}

Afzali-Kusha, A ^{[1
]}

Navabi, Z ^{[1
]}

机构：

[1] Univ Teheran, Elec & Comp Eng Dept, Low Power High Performance Nanosyst Lab, Tehran, Iran

来源：

42nd Design Automation Conference, Proceedings 2005 | 2005年

关键词：

switching activity; low power; signed multiplier; bus encoding; sing extension;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers based on this scheme, the dynamic power consumption of some digital systems such as digital filters based on CMOS logic system can be reduced considerably compared to those based on 2's complement implementation. To verify the efficacy of the SBR, a 16-bit multiplier was implemented by this scheme. The results for voice data show an average of 29% to 35% switching reduction compared to the 2's complement implementation. For 16-bit random data, this scheme decreases the switching of 16-bit multipliers by an average of 21%. Finally, the application of the technique to a 16-bit data bus leads up to 14.5% switching reduction on average.

引用

页码：214 / 217

页数：4

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