A High Performance Hardware Implementation Image Encryption With AES Algorithm

被引：4

作者：

Farmani, Ali ^{[1
]}

Jafari, Mohamad ^{[1
]}

Miremadi, Seyed Sohrab ^{[1
]}

机构：

[1] Univ Tabriz, Tabriz, Iran

来源：

THIRD INTERNATIONAL CONFERENCE ON DIGITAL IMAGE PROCESSING (ICDIP 2011) | 2011年 / 8009卷

关键词：

Advanced Encryption Standard(AES); Pipelining; Image Encryption; Decryption;

D O I：

10.1117/12.896659

中图分类号：

O43 [光学];

学科分类号：

070207 ; 0803 ;

摘要：

This paper describes implementation of a high-speed encryption algorithm with high throughput for encrypting the image. Therefore, we select a highly secured symmetric key encryption algorithm AES(Advanced Encryption Standard), in order to increase the speed and throughput using pipeline technique in four stages, control unit based on logic gates, optimal design of multiplier blocks in mixcolumn phase and simultaneous production keys and rounds. Such procedure makes AES suitable for fast image encryption. Implementation of a 128-bit AES on FPGA of Altra company has been done and the results are as follow: throughput, 6 Gbps in 471MHz. The time of encrypting in tested image with 32(*)32 size is 1.15ms.

引用

页数：7

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