Adaptive Forward Body Bias Voltage Generator

The performance of any analog or digital circuit is strongly dependent on threshold voltage (or turn on voltage) of transistors. The technology scaling does not significantly reduce the threshold voltage in the same proportion of aspect ratio of transistors. To overcome this challenge, forward body bias (FBB) technique is used to reduce the threshold voltage of transistors for enhancing the operating speed of device and operate them at low supply voltage at cost of forward biasing the bulk-drain or bulksource junction. In this brief, an adaptive FBB voltage generator is presented which tracks the process and temperature variations and accordingly modulates its output voltage. This adaptive FBB voltage also helps in reducing the static leakage through bulk as compared to fixed FBB voltage. The proposed design is simulated in 90mn BCD technology and reduces the threshold voltage by 48% for 1.2V LV (low voltage) NMOS and 34% for LV PMOS respectively at 25 degrees C. The proposed solution can be incorporated in digital signal processing (DSP) cores to increase the operating speed and periphery circuit of SRAM, DRAM and emerging NVM such as PCM, ReRAM & MRAM, to speed up the read path and reducing the access time. Furthermore, analog circuits can also take advantages of proposed solution to enhance the transconductance of transistors by reduction of threshold voltage.