Architecture and VLSI implementation of a programmable HD real-time motion estimator

被引：3
|
作者：
Gaedke, K. [1 ]
Borsurri, M. [1 ]
Georgi, M. [1 ]
Kluger, A. [1 ]
Le Glanic, J. -P. [2 ]
Bernard, P. [2 ]
机构：
[1] Thomson Corp Res, Hannover, Germany
[2] Thomson R&D, Rennes, France
来源：
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年
关键词：
D O I：
10.1109/ISCAS.2007.378826
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
The architecture and VLSI implementation of a programmable HD real-time motion estimator is presented. Due to the programmability, main video compression standards like MPEG-2, H.264, and VC-1 are supported. A sophisticated data flow concept in combination with a VLIW approach for controlling leads to a sustained utilization of the arithmetic resources of 95%. An area efficient architecture and design of the datapath consisting of 64 parallel processing elements reduced the required complexity to 1.2 million gates. With a first VLSI implementation in 90 nm standard cell semiconductor technology a maximum clock rate of 334 MHz was achieved. This design enables real-time motion estimation in HD format with 1920x1080 pixels at 25 Hz frame rate.
引用
收藏
页码：1609 / +
页数：2
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