A power-efficient architecture for high-speed D/A converters

被引：0
|
作者：
Farzan, K [1 ]
Johns, DA [1 ]
机构：
[1] Univ Toronto, ECE Dept, Toronto, ON M5S 3G4, Canada
来源：
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING | 2003年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel power-efficient architecture for high-speed D/A converters is proposed. A data look ahead technique is used to pre-switch the current sources so that the DAC current is reduced when generating small voltage levels. Interestingly, this technique also eliminates the need for a pre-driver block for each current-cell, which also saves power. Based on this architecture, a 6-bit DAC is designed in 0.18mum standard digital CMOS technology. The update rate for this DAC is 1GS/s and it consumes only 24mW at 1GS/s.
引用
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页码：897 / 900
页数：4
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