A 1GHz Configurable Chirp Modulation Direct Digital Frequency Synthesizer in 65nm CMOS

被引：1
|
作者：
Guo, Ting [1 ]
Tang, Kai [1 ]
Zheng, Yuanjin [1 ]
机构：
[1] Nanyang Technol Univ, Ctr Integrated Circuits & Syst, Singapore, Singapore
来源：
2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2021年
关键词：
direct digital frequency synthesizer (DDFS); chirp modulation (CM); frequency/phase accumulator; digital-to-analog convertor (DAC); time of chirp duration; pulse recurrence frequency (PRF);
D O I：
10.1109/ISCAS51556.2021.9401736
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 1GHz configurable chirp modulation (CM) direct digital frequency synthesizer (DDFS) is presented and implemented in 65nm CMOS technology. This DDFS is designed to generate 70-86MHz chirp signal for X-band frequency modulated continuous wave (FMCW) radar system. The proposed design is composed of 64-bit frequency control word (FCW) serial peripheral interface bus (SPI) supported 20-bit frequency/phase accumulator and 10-bit linear/non-linear hybrid digital-to-analog convertor (DAC). This DDFS supports saw-tooth chirp mode and exhibits 20-900 mu s time of chirp duration (TCD) and 1ms pulse recurrence frequency (PRF), dissipates 24mW@1GHz clock from a 1.2V supply. The DDFS core occupies 180 mu mx170 mu m area.
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页数：4
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