Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping

Technology scaling has enabled the fabrication of Multi-Processor Systems-on-Chips (MPSoCs), which satisfy the ever growing demand for performance, while continuously reducing the chip size. Thus, scaling has also led to new challenges such as increasing power densities, which critically influence the chip temperatures and accelerate device degradation due to aging. Runtime power management can be utilized to counter these reliability threats to increase the lifetime of a system. For the development of runtime power management strategies monitoring data for power, temperature and aging is required. In this paper we propose a real-time power, temperature and aging monitor system (eTAPMon) for FPGA prototypes of MP-SoCs. The monitor system emulates data characterized from the target ASIC design. The emulation approach models the behavior of ASIC power monitors based on an instruction-level energy model, temperature monitors based on a linear regression model obtained from thermal offline simulations and aging monitors based on a critical path model to compute the decreasing timing margin due to aging. An accelerated aging emulation is possible to predict aged ASIC behavior. Hence, this FPGA emulation enables the early evaluation of runtime power management strategies.