Characterization of nanoscale vertical-channel charge-trap memory thin film transistors using oxide semiconducting active and trap layers

We fabricated vertical-channel charge-trap memory thin film transistors (V-CTM TFTs) using an In-Ga-Zn-O channel and ZnO charge trap layers, in which a solution-processed SiO2 spacer pattern was introduced to scale down the vertical-channel length below 190 nm. The vertical gate-stack structure was implemented by atomic-layer deposition with excellent film conformality. The V-CTM TFTs with channel lengths of 190 (S1) and 140 nm (S2) showed charge-trap-assisted wide memory windows of 12.0 and 10.1 V, respectively. The memory margins between the on- and off-programmed currents were estimated to be 1.2 x 10(5) and 5.1 x 10(2) with a program pulse duration of 100 ms for S1 and S2, respectively. The programmed states did not exhibit any degradation with a lapse of retention for 10(4) s. With reducing the channel length, the number of endurance cycles decreased from 5000 to 3000 cycles. A vertical integration of oxide-based CTM device scaled down to sub-150 nm could be verified to show sound nonvolatile memory operations, even though there remain some technical issues such as a higher level of off-current for S2. Published under an exclusive license by the AVS.