A High Performance Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Refinement

被引：0

作者：

Correa, Marcel M. ^{[1
]}

Schoenknecht, Mateus T. ^{[1
]}

Agostini, Luciano V. ^{[1
]}

机构：

[1] UFPEL Fed Univ Pelotas, GACI Grp Architectures & Integrated Circuits, Pelotas, RS, Brazil

来源：

SBCCI 2010: 23RD SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2010年

关键词：

Video coding; H.264/AVC; Motion Estimation; Half-Pixel;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work presents a high performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation Refinement. This design can process very high definition videos like QHDTV (3840x2048) in real time processing (30 frames per second). It also presents a very optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The architecture was fully described in VHDL, synthesized to two different Xilinx FPGA devices and achieved the best results when compared to related works.

引用

页码：151 / 156

页数：6

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