An Adaptive Motion Estimation Architecture for H.264/AVC

We introduce a variable block size motion estimation architecture that is adaptive to the full search (FS) and the three-step search (3SS) algorithms. Early termination, intensive data reuse, pipelined datapath with bit serial execution, and memory access management tailored to the search patterns of the FS and 3SS form key features of the architecture. The design was synthesized using Synopsys Design Compiler and 45nm standard cell library technology. The architecture sustains real-time CIF format with an operational frequency as low as 17.6MHz and consumes 1.98 mW at this clock rate. This architecture with its 500MHz peak operational frequency provides the end-user with the flexibility of choosing between video quality and throughput based on power consumption and processing speed constraints.