A 120-Gbit/s 520-mVPP MULTIPLEXER IC USING 1-μm SELF-ALIGNED InP/InGaAs/InP DHBT WITH EMITTER MESA PASSIVATION LEDGE

被引：2

作者：

Arayashiki, Y. ^{[1
]}

Ohkubo, Y. ^{[1
]}

Matsumoto, T. ^{[1
]}

Koji, T. ^{[1
]}

Amano, Y. ^{[1
]}

Takagi, A. ^{[1
]}

Matsuoka, Y. ^{[1
]}

机构：

[1] Anritsu Devices Co Ltd, 5-1-1 Onna, Atsugi, Kanagawa 243855, Japan

来源：

2010 22ND INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS (IPRM) | 2010年

关键词：

SELECTOR;

D O I：

10.1109/ICIPRM.2010.5515958

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We fabricated 2: 1 multiplexer IC (MUX) with a retiming function by using 1-mu m self-aligned InP/InGaAs/InP double heterostructure bipolar transistors (DHBTs). As a result of the high performance DHBTs and the circuit design, in which we implemented broadband impedance matching, the MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and an output amplitude of 520 mV when measured on the wafer. The MUX was assembled in a module using V-connectors for practical use. In this module, the MUX operated at 113 Gbit/s with an output amplitude of 514 mW and a power dissipation of 1.4 W.

引用

页数：4

共 6 条

[1] A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation
Arayashiki, Yutaka
Ohkubo, Yukio
Matsumoto, Taisuke
Amano, Yoshiaki
Takagi, Akio
Matsuoka, Yutaka
[J]. IEICE TRANSACTIONS ON ELECTRONICS, 2010, E93C (08): : 1273 - 1278
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[6] High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-μm InP/InGaAs/InP Double Heterojunction Bipolar Transistors
Arayashiki, Yutaka
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Matsumoto, Taisuke
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Matsuoka, Yutaka
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