A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation

被引：3

作者：

Arayashiki, Yutaka ^{[1
]}

Ohkubo, Yukio ^{[1
]}

Matsumoto, Taisuke ^{[1
]}

Amano, Yoshiaki ^{[1
]}

Takagi, Akio ^{[1
]}

Matsuoka, Yutaka ^{[1
]}

机构：

[1] Anritsu Devices, Atsugi, Kanagawa 2438555, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2010年 / E93C卷 / 08期

关键词：

DHBT; self-aligned; ledge; MUX; broadband impedance matching; module;

D O I：

10.1587/transele.E93.C.1273

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-mu m self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.

引用

页码：1273 / 1278

页数：6

共 2 条

[1] A 120-Gbit/s 520-mVPP MULTIPLEXER IC USING 1-μm SELF-ALIGNED InP/InGaAs/InP DHBT WITH EMITTER MESA PASSIVATION LEDGE
Arayashiki, Y.
Ohkubo, Y.
Matsumoto, T.
Koji, T.
Amano, Y.
Takagi, A.
Matsuoka, Y.
[J]. 2010 22ND INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS (IPRM), 2010,
[2] Over 80 Gbit/s 2:1 multiplexer and low power selector ICs using InP/InGaAs DHBTs
Makon, RE
Lang, A
Driad, R
Schneider, K
Ludwig, A
Aidam, R
Quay, R
Schlechtweg, M
Weimann, G
[J]. ELECTRONICS LETTERS, 2005, 41 (11) : 644 - 646

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