Etch Process Optimization of Top Electrode of 1T1R RRAM

In this paper. we present a 1T1R (one-transistor one-resistor) structure RRAM (resistive switching random access memory) fully integrated with existing CMOS process. The RRAM cell is fabricated between two metal layers (metal A and metal B), and consists of plug contact type bottom electrode (plug-BE), resistive layer and top electrode (TE). As the RRAM cell is an island pattern, there are some issues in realistic fabrication process, such as TE bad CD uniformity, and TE metal D film missing (undercut) issue in TE/TE HM(hard-mask) etch process. Furthermore, the connection between RRAM cell TE and the upper metal layer (metal B) becomes challenge in metal B etch process due to the balance between removing HM remaining on RRAM TE and keeping the metal B trench depth to avoid metal B/RRAM cell bridge. In this contribution, we use temperature controllable method in TE HM etch step to improve the CD uniformity, and passivation gas method in TE etch to solve metal D undercut. For TE/metal B connection, the HM film is changed from oxide to NDC, which can be easily removed during metal B linear remove step without increasing the trench depth.