RDSP: A RISC DSP based on residue number system

被引：49

作者：

Chaves, R ^{[1
]}

Sousa, L ^{[1
]}

机构：

[1] INESC ID, IST, P-1000029 Lisbon, Portugal

来源：

EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/DSD.2003.1231911

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper is focused on low power programmable fast Digital Signal Processors (DSP) design based on a configurable 5-stage RISC core architecture and on Residue Number Systems (RNS). Several innovative aspects are introduced at the control and datapath architecture levels, which support both the binary system and the RNS. A new moduli set {2(n) - 1, 2(2n), 2(n) + 1} is also proposed for balancing the processing time in the different RNS channels. Experimental results, obtained trough RDSP implementation on FPGA and ASIC, show that not only a significant reduction in circuit area and power consumption but also a speedup may be achieved with RNS when compared with a binary DSP.

引用

页码：128 / 135

页数：8

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