ReCoNet: Modeling and implementation of fault tolerant distributed reconfigurable hardware

被引：4

作者：

Haubelt, C ^{[1
]}

Koch, D ^{[1
]}

Teich, E ^{[1
]}

机构：

[1] Univ Erlangen Nurnberg, Dept Como Sci 12, D-8520 Erlangen, Germany

来源：

16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/SBCCI.2003.1232851

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Recent research was mainly focused on the OS support for a single reconfigurable chip. This paper presents a general approach to manage fault tolerant distributed reconfigurable hardware. In order to run such a system, three basic tasks must be implemented: (i) rerouting to compensate line errors, (ii) rebinding to compensate node failures, and (iii) hardware reconfiguration to allow the optimization of these systems during runtime. This paper proposes first ideas and solutions of these management functions. Furthermore, a prototype implementation consisting of four fully connected FPGAs will be presented.

引用

页码：343 / 348

页数：6

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