Through-Silicon-Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs

被引：0

作者：

Kim, Dae Hyun ^{[1
]}

Mukhopadhyay, Saibal ^{[1
]}

Lim, Sung Kyu ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

11TH INTERNATIONAL WORKSHOP ON SYSTEM-LEVEL INTERCONNECT PREDICTION (SLIP 09) | 2009年

关键词：

TSV; Through Silicon Via; Interconnect Prediction; Wirelength Distribution; 3D IC; Rent's Rule;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Individual dies in 3D integrated circuits are connected using through-silicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power overhead. However, the effects of TSV overheads have not been studied thoroughly in the literature. In this paper, we analyze the impact of TSVs on silicon area and wirelength. We derive a new 3D wirelength distribution model considering TSV size. Based on this new prediction model, we explain the impact of several design parameters newly introduced in 3D ICs. We also present a case study to show how the model can help make early design decisions for 3D ICs.

引用

页码：85 / 92

页数：8

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