共 50 条
- [43] An Efficient Hardware Design Tool for Scalable Matrix Multiplication [J]. 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 1262 - 1265
- [46] Automated design of error-resilient and hardware-efficient deep neural networks [J]. NEURAL COMPUTING & APPLICATIONS, 2020, 32 (24): : 18327 - 18345
- [47] Automated design of error-resilient and hardware-efficient deep neural networks [J]. Neural Computing and Applications, 2020, 32 : 18327 - 18345
- [48] Error-Aware Design Procedure to Implement Hardware-Efficient Antilogarithmic Converters [J]. Circuits, Systems, and Signal Processing, 2019, 38 : 4266 - 4279
- [49] A hardware-efficient DAC for direct digital synthesis [J]. ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 97 - 100
- [50] Hardware-efficient architecture design of wavelet-based adaptive visible watennarking [J]. PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS 2005, 2005, : 399 - 403