Power optimized combinational logic design

被引：0

作者：

Menon, RV ^{[1
]}

Chennupati, S ^{[1
]}

Samala, NK ^{[1
]}

Radhakrishnan, D ^{[1
]}

Izadi, B ^{[1
]}

机构：

[1] SUNY Albany, Dept Elect & Comp Engn, New Paltz, NY 12561 USA

来源：

ESA'03: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS AND APPLICATIONS | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each gate. A powerful combinational logic optimization method using k-map is presented here that is based on disjoint implicants (implicates) of a function. More than 10% reduction in switching activity has been obtained with marginal increase in circuit area and delay.

引用

页码：223 / 227

页数：5

共 50 条

[1] COMBINATIONAL LOGIC DESIGN WITH DECODERS
GREER, CR
THOMPSON, RA
[J]. IEEE TRANSACTIONS ON COMPUTERS, 1978, 27 (09) : 869 - 875
[2] LOGIC DESIGN .2. COMBINATIONAL LOGIC
HOLDSWORTH, B
ZISSOS, L
[J]. WIRELESS WORLD, 1977, 83 (1494): : 49 - 53
[3] Design of Combinational Logic circuits for Low power Reversible Logic circuits in Quantum Cellular Automata
Anand, I. Vivek
Kamaraj, A.
[J]. 2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
[4] Combinational Logic Design in Synthetic Biology
Densmore, Douglas
Anderson, J. Christopher
[J]. ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 301 - +
[5] Genetic learning for combinational logic design
Louis, SJ
[J]. SOFT COMPUTING, 2005, 9 (01) : 38 - 43
[6] A SEQUENTIAL APPROACH TO COMBINATIONAL LOGIC DESIGN
PRICE, WL
[J]. RADIO AND ELECTRONIC ENGINEER, 1981, 51 (10): : 497 - 504
[7] Genetic learning for combinational logic design
S. J. Louis
[J]. Soft Computing, 2005, 9 : 38 - 43
[8] Design recovery for incomplete combinational logic
Doom, TE
Wojcik, AS
Chung, MJ
[J]. NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1999, : 184 - 187
[9] Power optimized logic circuit design with a novel synthesis technique
Balasubramanian, P
Narayana, MRL
Chinnaduari, R
[J]. IEEE: 2005 INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES, PROCEEDINGS, 2005, : 306 - 311
[10] State reordering for low power combinational logic
Tsai, KL
Lai, FP
Ruan, SJ
Chaung, SW
[J]. ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, 2003, 2823 : 268 - 276

← 1 2 3 4 5 →