Efficient Camera Input System and Memory Partition for a Vision Soft-Processor

One key issue in the design of Real-Time Image Processing and Computer Vision (IP/CV) systems is the massive volume of data to process. Not only the number of arithmetic and logic operations over the data but also the access to these data represents an important issue. An Application-Specific Instruction Set Processor (ASIP) focused on Real-Time IP/CV algorithms was developed in this work. Starting from a standard 32-bit Reduced Instruction Set Computer (RISC) as a benchmark, we analyzed the different issues and optimized the processor incrementally. We derived an economical image memory partition and also a new data path concept to speed up the processing. RTL models were synthesized for an FPGA, enabling an analysis of power consumption, area, and processing speed, to show the corresponding overheads in comparison with the original processor architecture.