Novel Sample Preparation Technique for Backside Analysis of Singulated Die

Backside techniques to isolate faults in integrated circuits are a common approach used by many failure analysts [1]. The increasing number of metallization layers of many semiconductor devices today makes backside analysis necessary. Traditionally, backside analysis involves parallel polishing the back of the package to thin and expose the die substrate. The sample is then biased in the failing mode using inverted micro-probes or an open socketed test board in the analytical tool of choice. The biased sample is then imaged in the near-infrared (NIR). One challenge facing failure analysts today is the continuously shrinking dimensions of semiconductor devices and a new generation of package technologies [2]. Semiconductor device packages are approaching the dimensions of the singulated die as evidenced by the increasing popularity of chip scale packages (CSP). CSP devices integrate the semiconductor die and connecting leads consisting of BGA (Ball Grid Array) or LGA (Land Grid Array) into a compact footprint within the size of the semiconductor die itself. Therefore, existing backside analysis techniques on CSP devices or singulated die are not feasible since no "package" exists to secure and mount the sample during inverted electrical testing without obscuring the active area of the die during NIR imaging. This paper discusses a novel and cost effective approach to perform backside analysis on a singulated die or CSP device.