Nyquist-Rate Time-Interleaved Current-Steering DAC with Dynamic Channel Matching

被引：0
|
作者：
Cheng, Long [1 ]
Ye, Fan [1 ]
Yang, Hai-Feng [1 ]
Li, Ning [1 ]
Xu, Jun [1 ]
Ren, Jun-Yan [1 ]
机构：
[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
来源：
2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2011年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A Nyquist-rate time-interleaved current-steering digital-to-analog converter (DAC) with dynamic channel matching (DCM) is proposed. Thanks to the proposed Nyquist-rate time-interleaved architecture, the DAC can properly operate at more than 1GS/s for a near-Nyquist output signal. The key limitation of the time-interleaved architecture is the mismatches between channels. The proposed DCM method can be applied to significantly suppress the spurious tones caused by imperfect channel matching. A 14-bit 1GS/s current-steering DAC with behavior models and a 0.18 mu m CMOS technology is simulated to illustrate the wideband time-interleaved architecture and the harmonic elimination of the DCM.
引用
收藏
页码：5 / 8
页数：4
相关论文
共 43 条
  • [31] Thermo data-weighted average dynamic element matching (DEM) encoder for current-steering DACs
    Wang, Yuan
    Liu, Baoguang
    Su, Wei
    Zhao, Junlei
    Zhang, Xing
    IEICE ELECTRONICS EXPRESS, 2013, 10 (20):
  • [32] A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection
    Lin, Wei-Te
    Kuo, Tai-Haur
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (02) : 444 - 453
  • [33] Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs
    Mehta, Shantanu
    O'Hare, Daniel
    O'Brien, Vincent
    Thompson, Eric
    Mullane, Brendan
    IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS, 2020, 1 : 34 - 47
  • [34] Robust design of a 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm CMOS
    程龙
    朱瑜
    朱凯
    陈迟晓
    任俊彦
    Journal of Semiconductors, 2013, 34 (10) : 125 - 131
  • [35] Robust design of a 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm CMOS
    程龙
    朱瑜
    朱凯
    陈迟晓
    任俊彦
    Journal of Semiconductors, 2013, (10) : 125 - 131
  • [36] Robust design of a 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm CMOS
    Cheng Long
    Zhu Yu
    Zhu Kai
    Chen Chixiao
    Ren Junyan
    JOURNAL OF SEMICONDUCTORS, 2013, 34 (10)
  • [37] The fast time-interleaved ADC channel mismatch calibration method based on equivalent sampling and dynamic reference point
    Xiang Qian
    Liu Hongqing
    Wu Hengkui
    Zhu Wenxing
    PROCEEDINGS OF 2019 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS (ICEMI), 2019, : 232 - 237
  • [38] A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration
    Fu, Yushen
    Huang, Chengyu
    Sun, Limeng
    Meng, Weiguang
    Li, Xueqing
    Yang, Huazhong
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 31 (02) : 199 - 209
  • [39] A 2.6-GS/s 8-bit Time-Interleaved ADC With Fully Dynamic Current Integrating Sampler
    Li, Dengquan
    Qian, Maowen
    Li, Depan
    Liang, Hongzhi
    Zhu, Zhangming
    IEEE SOLID-STATE CIRCUITS LETTERS, 2025, 8 : 29 - 32
  • [40] Time-Skew Error Correction in Two-Channel Time-Interleaved ADCs Based on a Two-Rate Approach and Polynomial Impulse Responses
    Kalidas, Anu
    Pillai, Muralidharan
    Johansson, Hakan
    2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2012, : 1136 - 1139
12345