Evaluation of shared DRAM for parallel processor system with shared memory

被引：0

作者：

Kurino, H ^{[1
]}

Hirano, K ^{[1
]}

Ono, T ^{[1
]}

Koyanagi, M ^{[1
]}

机构：

[1] Tohoku Univ, Grad Sch Engn, Dept Machine Intelligence & Syst Engn, Sendai, Miyagi 9808579, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 1998年 / E81A卷 / 12期

关键词：

multiport memory; shared memory; parallel processor system; DRAM;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We describe a new multiport memory which is called Shared DRAM (SHDRAM) to overcome bus-bottle neck problem in parallel processor system with shared memory. The processors are directly connected to this SHDRAM without conventional common bus. The test chip with 32 kbit memory cells is fabricated using a 1.5 mu m CMOS technology. The basic operation is confirmed by the circuit simulation and experimental results. In addition, it is confirmed by the computer simulation that the system performance with SHDRAM is superior to that with conventional common buses.

引用

页码：2655 / 2660

页数：6

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