A Fully Differential and Power-Efficient Difference Integrating ADC

This paper proposes an energy-efficient fully differential difference integrating analog-to-digital converter (ADC) for image sensors and biomedical recording systems where the variation of the input analog signal is usually much smaller than the full-scale range of the signal. In order to find the digital code of the input analog sample, the proposed structure digitizes the voltage difference between the new analog sample and the previous one, leading to power saving. The proposed ADC not only improves the rounding problem existing in the previous structures, but also its sampling rate is doubled by employing two auxiliary comparators. Moreover, using a segmented architecture for the employed capacitive-array digital-to-analog converter reduces the capacitor switching activity and therefore the power consumption of the ADC. The proposed ADC is designed and simulated in TSMC 0.18-mu m CMOS process. Post-layout simulation results of a 1-V, 8-bit, 40-kS/s ADC show that for low-varying input signals, the proposed circuit achieves a signal-to-noise-plus-distortion of 49.3 dB while consuming 220 nW power dissipation, leading to a figure of merit of 23 fJ/c-step. The silicon area occupied by the circuit is 300 mu m x 215 mu m.