Baseband processor for impulse ultra-wideband communications

This paper presents a baseband processor architecture for pulsed ultra-wideband signals. It consists of an analog-to-digital converter (ADC), a clock generation system, and a digital back-end. The clock generation system provides different phases of a 300-MHz clock using four differential inverter stages. The specification of the jitter standard deviation is 100 ps. The Flash interleaved ADC provides four bit samples at 1.2 Gsps. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 65 ps. The entire synchronization algorithm is implemented in the digital domain, without feeding any signals back to the clock control. The baseband processor and ADC were implemented on the same 0.18-mu m CMOS die at 1.8 V as part of a complete baseband transceiver. A wireless data rate of 193 kb/s is demonstrated.