Fine-grained hardware switching scheme for power reduction in multiplication

被引：0
|
作者：
Huang, Y. [1 ,2 ]
Li, C. [1 ,2 ]
Li, M. [1 ]
Van der Perre, L. [2 ]
Dehaene, W.
机构：
[1] IMEC, Leuven, Belgium
[2] Katholieke Univ Leuven, ESAT Dept, Leuven, Belgium
来源：
ELECTRONICS LETTERS | 2016年 / 52卷 / 16期
关键词：
D O I：
10.1049/el.2015.3828
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This Letter presents a fine-grained hardware switching scheme to choose from the proper hardware for low power computing. It exploits the word-length optimisation opportunities for multiplication unit. With the proposed technique, the gate-level simulation result on OpenRISC shows 23.7% power reduction for the multiplication unit, which accounts for 9.5% power reduction for its execution unit.
引用
收藏
页码：1374 / 1375
页数：2
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