Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller

被引：2
|
作者：
Boncalo, Oana [1 ]
Amaricai, Alexandru [1 ]
Lendek, Zsofia [2 ]
机构：
[1] Univ Politehn Timisoara, Timisoara, Romania
[2] Tech Univ Cluj Napoca, Cluj Napoca, Romania
来源：
2019 22ND EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD) | 2019年
关键词：
Fuzzy control; robot arm control; FPGA acceleration; IMPLEMENTATION; SYSTEMS;
D O I：
10.1109/DSD.2019.00024
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
In this paper, we present a parametric hardware accelerator for Takagi-Sugeno fuzzy controllers. The architecture consists of an application specific weighting function computation block, generic control output computation unit, and a programmable register file based interface. The proposed hardware design methodology is applied to a two degree of freedom robot arm controller. FPGA implementation results indicate that the hardware TS fuzzy controller supports throughputs up to 1.5 Msamples/sec, with maximum working frequencies of around 150 MHz.
引用
收藏
页码：96 / 101
页数：6
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