We report on progress in improving fundamental properties of InP-based single photon avalanche diodes (SPADs) and recent trends for overcoming dominant performance limitations. Through experimental and modeling work focused on the trade-off between dark count rate (DCR) and photon detection efficiency (PDE), we identify the key mechanisms responsible for DCR over a range of operating temperatures and excess bias voltages. This work provides a detailed description of temperature-and bias-dependent DCR thermal activation energy E-a(T, V), including the crossover from low E-a for trap-assisted tunneling at temperatures below similar to 230 K to larger E-a for thermal generation at temperatures approaching room temperature. By applying these findings to new device design and fabrication, the fundamental tradeoff between PDE and DCR for InP/InGaAs SPADs designed for 1.55 mu m photon detection has been managed so that for PDE similar to 20%, devices routinely exhibit DCR values of a few kHz, while "hero" devices demonstrate that it is possible to achieve sub-kHz DCR performance at temperatures readily accessible using thermoelectric coolers. However, important limitations remain, particularly with respect to maximum count rates. Strategies adopted recently to circumvent some of these present limitations include new circuit-based solutions involving high-speed very shortduration gating as well as new monolithic chip-level concepts for obtaining improved performance through avalanche self-quenching. We discuss these two approaches, and we describe recent results from devices with monolithically integrated quench resistors that achieve rapid self-quenching, accompanied by evidence for a partial discharge of the detector capacitance leading to charge flows as low as similar to 3 x 10(5) carriers associated with each avalanche event.