Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time

被引：0

作者：

Simacek, Jiri ^{[1
]}

Sekanina, Lukas ^{[1
]}

Starecek, Lukas ^{[1
]}

机构：

[1] Brno Univ Technol, Fac Informat Technol, Brno 61266, Czech Republic

来源：

EVOLVABLE SYSTEMS: FROM BIOLOGY TO HARDWARE | 2010年 / 6274卷

关键词：

SCAN; COMPACTION;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Recently, a method has been presented that allows a significant test application time reduction if some of gates of a digital circuit are reconfigured before test is applied. Selection of the gates for reconfiguration was performed using a very time consuming deterministic recursive search algorithm. In this paper, a new method is proposed for selection of the gates in order to reduce the test application time. The method utilizes an evolutionary algorithm which is able to discover very competitive reconfiguration strategies while the time of optimization is considerably reduced with respect to the original algorithm. Moreover, the user can easily balance the trade off between the number of test vectors and amount of logic that has to be reconfigured. Experimental results are reported for the ISCAS85 benchmark suite.

引用

页码：214 / 225

页数：12

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