Design for Architecture and Router of 3D Free-Space Optical Network-on-Chip

Nowadays, owing to the advantages of high bandwidth and low power consumption, the wired optical network-on-chip (W-ONoC) has emerged as a high-performance on-chip communication solution. However, the W-ONoC suffers from increased latency and limited scalability since the multi-hop data transmission is frequently performed in wired structures. In addition, several problems such as photoelectric conversion and thermal sensitivity pose challenges to the design of W-ONoCs. In this paper, we develop a novel on-chip communication architecture based on free-space optics (FSO), and leverage a suite of emerging devices. The proposed architecture eliminates the power loss caused by the waveguide and microring resonator previously deployed in W-ONoCs, and the transmission latency is also reduced through simplifying the packet switching. Moreover, compared with the traditional single-layer FSO NoC, our 3D FSO NoC further decreases the number of consumed lasers and power. Extensive simulation results demonstrate the aforementioned advantages of our solution.