InTeRail: A test architecture for core-based SOCs

被引：2
|
作者：
Kagaris, D [1 ]
Tragoudas, S [1 ]
Kuriakose, S [1 ]
机构：
[1] So Illinois Univ, Dept Elect & Comp Engn, Carbondale, IL 62901 USA
来源：
IEEE TRANSACTIONS ON COMPUTERS | 2006年 / 55卷 / 02期
关键词：
system-on-chip test; cores; test access mechanism; design for testability;
D O I：
10.1109/TC.2006.27
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A flexible test architecture for embedded cores and all interconnects in a System-on Chip (SOC) is presented. It targets core testing parallelism and reduced test application time by using, as much as possible, existing core interconnects to form TAM paths. It also provides for dynamic wrapper reconfiguration. Algorithms that minimize the use of extra interconnects for the TAM path formation are presented and evaluated.
引用
收藏
页码：137 / 149
页数：13
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