Follow me - Digital jitter measurement method

This paper consists description of research results regarding digital jitter measurements for higher data rates. In previous publications [1][2][3] author has investigated different methods of digital jitter measurements, however they were applicable for data streams with lower clock frequencies. Developed methods and algorithms were optimised for implementation in FPGAs or ASICs. This work consists description of novel digital jitter measurement technique using programmable clock generators with phase shifters. Tests of this method were performed on well-known FPGA chips however may be easily extended to other digital environments. Obtained results are very promising; whole system may by integrated in one chip, measurement accuracy and resolution is pretty good and solution is easily scalable.