A Low-Power 64x64 ASIC 2-Bit Digital Correlator

被引:0
|
作者
Austerberry, David C. [1 ]
McKague, Darren S. [1 ]
Ruf, Christopher S. [1 ]
机构
[1] Univ Michigan, Ann Arbor, MI 48109 USA
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
引用
收藏
页码:292 / 292
页数:1
相关论文
共 50 条
  • [21] A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices
    Foley, Denis
    Bansal, Pankaj
    Cherepacha, Don
    Wasmuth, Robert
    Gunasekar, Aswin
    Gutta, Srinivasa
    Naini, Ajay
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (01) : 220 - 231
  • [22] 64-bit reconfigurable adder for low power media processing
    Perri, S
    Corsonello, P
    Cocorullo, G
    ELECTRONICS LETTERS, 2002, 38 (09) : 397 - 399
  • [23] A CMOS 0.18μm 64x64 Single Photon Image Sensor with In-Pixel 11b Time-to-Digital Converter
    Vornicu, I.
    Carmona-Galan, R.
    Rodriguez-Vazquez, A.
    2014 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), 2014, : 131 - 134
  • [24] Low-power mixed-signal CVNS-based 64-bit adder for media signal processing
    Mirhassani, Mitra
    Ahmadi, Majid
    Jullien, Graham A.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (09) : 1141 - 1150
  • [25] A 64 kB Approximate SRAM Architecture for Low-Power Video Applications
    Ataei, Samira
    Stine, James E.
    IEEE EMBEDDED SYSTEMS LETTERS, 2018, 10 (01) : 10 - 13
  • [26] A LOW-POWER RESISTIVE LOAD 64 KBIT CMOS-RAM
    UCHIDA, Y
    IIZUKA, T
    MATSUNAGA, J
    ISOBE, M
    KONISHI, S
    SEKINE, M
    OHTANI, T
    KOHYAMA, S
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (05) : 804 - 809
  • [27] An ASIC for Energy-Scalable, Low-Power Digital Ultrasound Beamforming
    Lam, Bonnie
    Price, Michael
    Chandrakasan, Anantha P.
    2016 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 2016, : 57 - 62
  • [28] Low-power design of a 64-tap, 4-bit Digital Matched Filter using Systolic Array architecture and CVSL circuit techniques in CMOS
    Yalcin, T
    Ismailoglu, N
    CONFERENCE RECORD OF THE THIRTY-SECOND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 1998, : 1066 - 1069
  • [29] A Very Low Power 12 bit 64-MS/s 2 step SAR Assisted Bidirectional Digital Slope ADC
    Casanova, Jean-Baptiste
    Perrin, Danika
    Nicolas, Sandrine
    Kaiser, Andreas
    2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS, 2023,
  • [30] A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator
    Chuang, Pierce
    Li, David
    Sachdev, Manoj
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2012, 59 (02) : 108 - 112