Modeling of DRAM power control policies using deterministic and stochastic Petri nets

Modern DRAM technologies offer power management features for optimization between performance and energy consumption. This paper employs Petri nets to model and evaluate memory controller policies for manipulating multiple power states. The model has been validated against the analysis and simulation used in our previous work. We extend it to model more complex policies and our results show that DRAM chip should always immediately transition to standby and never transition to powerdown provided that it exhibits typical exponential access behavior.